23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10-12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2].

[1]  Thomas Toifl,et al.  10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Behzad Razavi,et al.  A 40-Gb/s 9.2-mW CMOS equalizer , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[3]  W. Walker,et al.  A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  Vishnu Balan,et al.  26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).