Optimising the SHA-512 cryptographic hash function on FPGAs

In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors.