Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability

In response to the rising fault susceptibility of ICs due to aggressive device scaling, a number of concurrent error detection (CED) techniques have been proposed. Most existing techniques address the problem at device or logic level. To account for the significant process variations and device aging of today's nano-meter devices, these techniques must always aim at the worst case of fault susceptibility. Recognizing that the power consumption of the CED circuitry for different fault susceptibility varies significantly, these techniques could result in significant overhead. In this paper, we propose register transfer level CED techniques that can be adjusted at runtime according to the actual need. The proposed high-level synthesis technique ensures that the generated datapath consumes minimal power for any CED capability it has been turned to. The proposed approach is tested using known benchmarks.

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