论文信息 - Implementation of 5 - 32 Bit Decoder using NAND Logic at 180 nm & 350 nm Technologies for High Speed Memory Applications - 字舞流文

Implementation of 5 - 32 Bit Decoder using NAND Logic at 180 nm & 350 nm Technologies for High Speed Memory Applications

Anshika Sharma | Ashok Pandey | Abhinav Vishnoi | Pankaj Bhardwaj

[1] I. Sutherland,et al. Logical Effort: Designing Fast CMOS Circuits , 1999 .

[2] Bharadwaj Amrutur,et al. Fast low-power decoders for RAMs , 2001, IEEE J. Solid State Circuits.

[3] J.G. Delgado-Frias,et al. Reducing power in memory decoders by means of selective precharge schemes , 2007, 2007 50th Midwest Symposium on Circuits and Systems.