Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determines the drain current. The model is supported by experimental measurements in JL nanowire transistors with channel length varying from 95 to 25 nm and doping concentration 2 x 1019 cm-3. The overall results reveal the very good accuracy of the proposed analytical compact model, making it suitable for circuit simulation tools.

[1]  R. K. Baruah,et al.  A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor , 2016 .

[2]  J. Hwu,et al.  Effect of interface traps related to mobile charges on silicon n-channel metal/oxide/semiconductor field effect transistors determined by a charge-temperature technique , 1986 .

[3]  A. Gnudi,et al.  Numerical investigation on the junctionless nanowire FET , 2011, Ulis 2011 Ultimate Integration on Silicon.

[4]  Alexander Kloes,et al.  3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs, including simple treatment of quantization effects , 2015 .

[5]  Marcelo Antonio Pavanello,et al.  Compact core model for Symmetric Double-Gate Junctionless Transistors , 2014 .

[6]  A. Gnudi,et al.  Theory of the Junctionless Nanowire FET , 2011, IEEE Transactions on Electron Devices.

[7]  Mansun Chan,et al.  Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs , 2016, IEEE Transactions on Electron Devices.

[8]  O. Faynot,et al.  Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm , 2012, IEEE Electron Device Letters.

[9]  M. de Souza,et al.  Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors , 2012, IEEE Transactions on Electron Devices.

[10]  G. Ghibaudo,et al.  Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[11]  Ahmed F. Abo-Elhadeed,et al.  Compact model for short and ultra thin symmetric double gate , 2010, 2010 International Conference on Microelectronics.

[12]  Sungho Kim,et al.  A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model , 2013, IEEE Transactions on Electron Devices.

[13]  Sylvain Barraud,et al.  Low-temperature electrical characterization of junctionless transistors , 2013 .

[14]  J. Dorkel,et al.  Carrier mobilities in silicon semi-empirically related to temperature, doping and injection level , 1981 .

[15]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[16]  Sung-Jin Choi,et al.  Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors , 2011, IEEE Electron Device Letters.

[17]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[18]  G. Ghibaudo,et al.  Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[19]  G. Ghibaudo,et al.  Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control , 2015, IEEE Transactions on Electron Devices.

[20]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[21]  Jean-Michel Sallese,et al.  Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime , 2013 .

[22]  Bruna Cardoso Paz,et al.  Charge-based compact analytical model for triple-gate junctionless nanowire transistors , 2016 .

[23]  Sung-Jin Choi,et al.  A Full-Range Drain Current Model for Double-Gate Junctionless Transistors , 2011, IEEE Transactions on Electron Devices.

[24]  Seok-Hee Lee,et al.  Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors , 2015, IEEE Transactions on Electron Devices.

[25]  G. Ghibaudo,et al.  Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs , 2012, IEEE Transactions on Electron Devices.

[26]  Giuseppe Iannaccone,et al.  Compact drain-current model for reproducing advanced transport models in nanoscale double-gate MOSFETs , 2011 .

[27]  Minghua Tang,et al.  Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs , 2012, IEEE Transactions on Electron Devices.

[28]  Sebastien Haendler,et al.  Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction , 2015 .

[29]  Yuan Taur,et al.  A framework for generic physics based double-gate MOSFET modeling , 2003 .