Triple density DRAM cell with Si selective growth channel and NAND-structure

We propose a novel trench capacitor cell suitable for shrinkage, named triple density cell (TD-cell). The TD-cell has a planar transistor which overhangs a storage trench capacitor, and Si selective epitaxial growth (SEG) is used for channel formation. The cell size reduces to ultimately 33% for the conventional folded-bit-line arrangement, by combining this stacked configuration and NAND-structured cell arrangement. We also verified and analyzed threshold and sub-threshold transport for transistors made on SEG Si layer.<<ETX>>