A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS

A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mode logic (CML) was fabricated in a 130-nm bulk complementary metal-oxide semiconductor (CMOS) logic process. By optimizing transistors size, high operating speed is achieved with limited power consumption. For an input power of 0dBm, the 32:1 divider operates up to 26GHz with a 1.5-V supply voltage. The whole 32:1 chain including buffers consumes 8.97mW and the first stage consumes only 3.88mW at a 26-GHz operation. The power consumption of the first 2:1 stage is less than 15% of other bulk CMOS static frequency dividers operating at the same frequency.

[1]  Jean-Olivier Plouchart,et al.  A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS , 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.

[2]  M. Fujishima,et al.  4.3 GHz 44 /spl mu/W CMOS frequency divider , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Yuan Taur,et al.  SOI and bulk CMOS frequency dividers operating above 15 GHz , 2001 .

[4]  K.A. Jenkins,et al.  A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider , 2000, IEEE Microwave and Guided Wave Letters.

[5]  H.-D. Wohlmuth,et al.  A high sensitivity static 2:1 frequency divider up to 27GHz in 120nm CMOS , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[6]  Herbert Knapp,et al.  17.9 25GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12µm CMOS , 2002 .

[7]  Jri Lee,et al.  A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology , 2004, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[8]  Z. Griffith,et al.  87 GHz static frequency divider in an InP-based mesa DHBT technology , 2002, 24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu.

[9]  M. Wurzer,et al.  86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology , 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

[10]  W. Simburger,et al.  A high sensitivity static 2:1 frequency divider up to 19 GHz in 120 nm CMOS , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[11]  Charles G. Sodini,et al.  A 200 MHz CMOS phase-locked loop with dual phase detectors , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[12]  A. Hajimiri,et al.  A 19 GHz 0.5 mW 0.35 /spl mu/m CMOS frequency divider with shunt-peaking locking-range enhancement , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).