A feasibility study of master-slave flipflop design for hexadecimal logic

The feasibility of flipflop designs for storing hexadecimal datum is studied in this work. Hexadecimal signal processing appears the benefit on the great reduction of interconnections, which leads to the potential of improving various performances. However, the storage of hexadecimal datum is very challenging for the conventional binary implementations. In this paper, a prototype of hexadecimal flipflop circuit based on self-latched loop is proposed by the standard CMOS process and ordinary dual-rail power supply. The Neuron-MOS technology is employed to implement inverters with multiple threshold values. The self-latched loop is designed by coupling a compact hexadecimal-to-binary inverter and a binary-to-hexadecimal inverter. This type of flipflop is adaptable to both of hexadecimal and binary input/output forms. For verifying the proposed circuits, the sixteen-counter is demonstrated by the proposed hexadecimal flipflop circuit in a master-slave fashion. The number of transistors is reduced to 81.6% of a sixteen-counter consisting of four naive binary master-slave flipflops. From the circuit simulation results, the sixteen-counter employing the proposed master-slave hexadecimal flipflop circuit behaves the counting function correctly.

[1]  Jonathan Rose,et al.  On the difficulty of pin-to-wire routing in FPGAs , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[2]  Svetlana N. Yanushkevich,et al.  Technique of computing logic derivatives for MVL-functions , 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

[3]  K. Chalasinska-Macukow.  Analog pattern recognition processors for transparent optical network , 2002, Proceedings of 2002 4th International Conference on Transparent Optical Networks (IEEE Cat. No.02EX551).

[4]  Sang-Bock Cho,et al.  Design of an 8-bit neuron MOSFET A/D converter using subranging method , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[5]  T. Nakamura,et al.  Realization of quaternary logic circuits by n-channel MOS devices , 1986 .

[6]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[7]  Paulo F. Flores,et al.  Quaternary Logic Lookup Table in Standard CMOS , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Nilanjan Chattaraj,et al.  Random Access Analog Memory (RA2M) for Video Signal Application , 2012, 2012 25th International Conference on VLSI Design.

[9]  Mineo Kaneko,et al.  An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors , 2014 .

[10]  Yongwang Zhao,et al.  Medical Image Retrieval with Query-Dependent Feature Fusion Based on One-Class SVM , 2010, 2010 13th IEEE International Conference on Computational Science and Engineering.

[11]  Daniel Etiemble,et al.  Comparison of binary and multivalued ICs according to VLSI criteria , 1988, Computer.

[12]  Fatma Sarica,et al.  Basic circuits for multi-valued sequential logic , 2011, 2011 7th International Conference on Electrical and Electronics Engineering (ELECO).

[13]  Vasundara Patel K.S.,et al.  Quaternary CMOS Combinational Logic Circuits , 2009, 2009 International Conference on Information and Multimedia Technology.

[14]  Kenneth C. Smith.  The Prospects for Multivalued Logic: A Technology and Applications View , 1981, IEEE Transactions on Computers.

[15]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[16]  Xiaohu You,et al.  Quaternary edge-triggered flip-flop with neuron-MOS literal circuit , 2013, 2013 Ninth International Conference on Natural Computation (ICNC).

[17]  Bo Wang,et al.  Ultra-low power 12T dual port SRAM for hardware accelerators , 2014, 2014 International SoC Design Conference (ISOCC).

[18]  Yulei Zhang,et al.  Performance Comparison and Overview of Different Approaches for VLSI Optoelectronic Interconnects , 2010, IEEE/OSA Journal of Optical Communications and Networking.

[19]  Hiroshi Murase,et al.  Power-Efficient Hardware Architecture of K-Means Clustering With Bayesian-Information-Criterion Processor for Multimedia Processing Applications , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[20]  Mineo Kaneko,et al.  A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[21]  Michitaka Kameyama,et al.  A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic , 1995 .

[22]  Turgay Temel,et al.  Multi-valued logic function implementation with novel current-mode logic gates , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[23]  G. Kanaan,et al.  Support vector machine text classification system: Using Ant Colony Optimization based feature subset selection , 2008, 2008 International Conference on Computer Engineering & Systems.

[24]  Kaushik Roy,et al.  Approximate computing: An integrated hardware approach , 2013, 2013 Asilomar Conference on Signals, Systems and Computers.

[25]  Jong-In Song,et al.  Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count , 2013, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013).