A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application
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Xiaoqing Wen | Zhengfeng Huang | Kang Yang | Xiangsheng Fang | Maoxiang Yi | Jiliang Zhang | Aibin Yan | Jie Cui | Jiliang Zhang | X. Wen | Zhengfeng Huang | Maoxiang Yi | Aibin Yan | Xiangsheng Fang | Kang Yang | Jie Cui
[1] Spyros Tragoudas,et al. Radiation Hardened Latch Designs for Double and Triple Node Upsets , 2017, IEEE Transactions on Emerging Topics in Computing.
[2] Yiorgos Tsiatouhas,et al. Soft error interception latch: double node charge sharing SEU tolerant design , 2015 .
[3] P. Reviriego,et al. Reliability Analysis of Memories Suffering Multiple Bit Upsets , 2007, IEEE Transactions on Device and Materials Reliability.
[4] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[5] Xu Hui,et al. Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches , 2015, IEICE Electron. Express.
[6] Yuanqing Li,et al. Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..
[7] Bahar Asgari,et al. Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies , 2015, IEEE Transactions on Device and Materials Reliability.
[8] Lawrence T. Clark,et al. Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection , 2015, IEEE Transactions on Nuclear Science.
[9] Huaguo Liang,et al. HLDTL: High-performance, low-cost, and double node upset tolerant latch design , 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).
[10] Huaguo Liang,et al. High-performance, low-cost, and highly reliable radiation hardened latch design , 2016 .
[11] Huaguo Liang,et al. A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..
[12] Kiamal Z. Pekmestzi,et al. DONUT: A Double Node Upset Tolerant Latch , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.
[13] Maryam Shojaei Baghini,et al. Robust Soft Error Tolerant CMOS Latch Configurations , 2016, IEEE Transactions on Computers.
[14] Jaspal Singh Shah,et al. A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS , 2015, IEEE Transactions on Nuclear Science.
[15] Jiliang Zhang,et al. A Practical Logic Obfuscation Technique for Hardware Security , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Ken Choi,et al. High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[17] P. E. Dodd,et al. Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.
[18] Huaguo Liang,et al. Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] T.M. Mak,et al. Built-In Soft Error Resilience for Robust System Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.
[20] Kostas Tsoumanis,et al. Delta DICE: A Double Node Upset resilient latch , 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).
[21] Ahmad Patooghy,et al. Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).
[22] Huaguo Liang,et al. A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..
[23] Cecilia Metra,et al. High-Performance Robust Latches , 2010, IEEE Transactions on Computers.
[24] Fabrizio Lombardi,et al. Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.