An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable System-on-Chip

This paper proposes a network-on-chip architecture that offers high flexibility and performance. It is used in a system-on-chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial implementation results for a network router show its feasibility and size comparable with other available solutions.

[1]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[2]  H. Zhang,et al.  A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  William J. Dally.  Virtual-Channel Flow Control , 1992, IEEE Trans. Parallel Distributed Syst..

[4]  Gerardus Johannes Maria Smit,et al.  A Survey of Efficient On-Chip Communications for SoC , 2003 .

[5]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[6]  Gerard J. M. Smit,et al.  A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems , 2003, The Journal of Supercomputing.

[7]  Paul J. M. Havinga,et al.  Dynamic Reconfiguration in Mobile Systems , 2002, FPL.

[8]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[9]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[10]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[11]  Gerard J. M. Smit,et al.  Implementation of a HiperLAN/2 receiver on the reconfigurable Montium architecture , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..