A unifying formalism to support automated synthesis of SBSTs for embedded caches

The paper presents a new unifying formalism introduced to effectively support the automatic generation of assembly test programs to be used as SBST (Software Based Self-Testing) for both data and instruction cache memories. In particular, the new formalism allows the description of the target memory, of the selected March Test algorithm, and the way this has to be customize to adapt it to the selected cache.

[1]  Sandeep K. Gupta,et al.  A methodology for transforming memory tests for in-system testing of direct mapped cache tags , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[2]  Alessandro Savino,et al.  Software-Based Self-Test of Set-Associative Cache Memories , 2011, IEEE Transactions on Computers.

[3]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[4]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[5]  Paolo Prinetto,et al.  MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches , 2011, 2011 Asian Test Symposium.

[6]  Said Hamdioui,et al.  The state-of-art and future trends in testing embedded memories , 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

[7]  Frank Vahid,et al.  A highly configurable cache architecture for embedded systems , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[8]  S. Hamdioui,et al.  Converting March tests for bit-oriented memories into tests for word-oriented memories , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[9]  Paolo Prinetto,et al.  Models in Memory Testing , 2010 .

[10]  J. Sosnowski,et al.  Improving Software Based Self - Testing for Cache Memories , 2007, 2007 2nd International Design and Test Workshop.

[11]  Janusz Sosnowski.  In-system testing of cache memories , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).