Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

This paper addresses the problem of delay and power minimization in transmitting a signal along a distance in wire segments in field-programmable gate arrays (FPGAs). With the continuous scaling of the IC technology node, while transistors become faster, wires become slower. Delay and power are considered to be the most important issues in designing FPGAs. In FPGAs, crossing signals can exit from the end of wire segments or exit from somewhere before the end point via Early Turns. This paper presents an efficient method for obtaining optimum places for Early Turns, and then reducing two types of delays including the expected delay, and the end-to-end delay. Also by using this method power can be reduced. A method has been proposed to reduce the FPGAs delay and power in wire segmentations by buffer insertion while choosing the best size and place for the buffers. We present a technique to find Early Turn points as proper places for buffer insertion. Simulation results for the 45nm technology node prove that the expected delay of the proposed wire segmentation structure has up to 53% better performance compared with the buffered interconnects constructed with only the end-to-end delay optimization. Also our results show that when the power optimization is performed based on the expected power, the power is improved 46% compared with the case that only the end-to-end power is optimized.

[1]  Yehea Ismail,et al.  Optimum positioning of interleaved repeaters in bidirectional buses , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Seda Ogrenci Memik,et al.  A low power FPGA routing architecture , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  Shahriar Mirabbasi,et al.  Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays , 2008, J. Signal Process. Syst..

[4]  Martin D. F. Wong,et al.  A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Wayne Luk,et al.  An energy and power consumption analysis of FPGA routing architectures , 2009, 2009 International Conference on Field-Programmable Technology.

[6]  Zvonko G. Vranesic,et al.  Minimizing interconnection delays in array-based FPGAs , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[7]  Madhav P. Desai,et al.  Interconnect delay minimization using a novel pre-mid-post buffer strategy , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[8]  Mohammad Tohidi,et al.  Interconnect design in nanoscale FPGAs , 2010, 2010 3rd International Nanoelectronics Conference (INEC).

[9]  Kundan Nepal,et al.  Low-power FPGA routing switches using adaptive body biasing technique , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[10]  Magdy A. Bayoumi,et al.  Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[12]  Anthony J. Yu,et al.  Directional and single-driver wires in FPGA interconnect , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[13]  N. Masoumi,et al.  Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization , 2008, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era.

[14]  S. D. Pable,et al.  High speed interconnect through device optimization for subthreshold FPGA , 2011, Microelectron. J..

[15]  Fei Li,et al.  Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[16]  Jason Cong,et al.  Simultaneous buffer and wire sizing for performance and power optimization , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[17]  Mark A. Franklin,et al.  Optimum buffer circuits for driving long uniform lines , 1991 .

[18]  Nasser Masoumi,et al.  A stochastic evaluation methodology for wire segmentation in FPGAs for optimum performance , 2011, 2011 19th Iranian Conference on Electrical Engineering.

[19]  Philip Heng Wai Leong,et al.  A detailed delay path model for FPGAs , 2009, 2009 International Conference on Field-Programmable Technology.

[20]  Stephen Dean Brown,et al.  Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Nasser Masoumi,et al.  An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies , 2009, 2009 European Conference on Circuit Theory and Design.

[22]  Wai-Kei Mak,et al.  Optimal Buffering of FPGA Interconnect for Expected Delay Optimization , 2007, 2007 International Conference on Field-Programmable Technology.

[23]  Rui Tu,et al.  Energy/Performance/Area Tradeoffs in Nanometer FPGA Segmented Routing Architecture , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[24]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[25]  Charlie Chung-Ping Chen,et al.  Optimal wire-sizing formula under the Elmore delay model , 1996, DAC '96.

[26]  Chung-Ping Chen,et al.  A fast algorithm for optimal wire-sizing under Elmore delay model , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[27]  M. Mehran,et al.  A tapered partitioning method for “delay energy product” optimization in global interconnects , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[28]  David Eppstein,et al.  Interconnect Criticality-Driven Delay Relaxation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Ross Baldick,et al.  A sequential quadratic programming approach to concurrent gate and wire sizing , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Kaustav Banerjee,et al.  A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .

[31]  Jason Helge Anderson,et al.  Low-Power Programmable FPGA Routing Circuitry , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Jason Helge Anderson,et al.  A novel low-power FPGA routing switch , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).