Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024/spl times/144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 /spl mu/m CMOS process.

[1]  A. Sheikholeslami,et al.  A current-saving match-line sensing scheme for content-addressable memories , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[2]  Ali Sheikholeslami,et al.  A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme , 2003, IEEE J. Solid State Circuits.

[3]  K. J. Schultz,et al.  Fully Parallel 30-MHz , 2 . 5-Mb CAM , 1998 .

[4]  Lawrence Chisvin,et al.  Content-addressable and associative memory: alternatives to the ubiquitous RAM , 1989, Computer.

[5]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[6]  C. A. Zukowski,et al.  Use of selective precharge for low-power content-addressable memories , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[7]  C. Zukowski,et al.  Putting routing tables in silicon , 1992, IEEE Network.

[8]  Hisatada Miyatake,et al.  A design for high-speed low-power CMOS fully parallel content-addressable memory macros , 2001 .