Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Abstract Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

[1]  Karl Hess,et al.  Simulation of Si-SiO/sub 2/ defect generation in CMOS chips: from atomistic structure to chip failure rates , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[2]  Tibor Grasser,et al.  Interface traps density-of-states as a vital component for hot-carrier degradation modeling , 2010, Microelectronics and reliability.

[3]  Pierpaolo Palestri,et al.  On the accuracy of current TCAD hot carrier injection models in nanoscale devices , 2010 .

[4]  Karl Hess,et al.  A Multi-Carrier Model for Interface Trap Generation , 2002 .

[5]  M. Tack,et al.  A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[6]  Karl Hess,et al.  MOSFET degradation kinetics and its simulation , 2003 .

[7]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[8]  C.M. Liu,et al.  On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region , 2008, IEEE Electron Device Letters.

[9]  W. Fichtner,et al.  Surface mobility in silicon at large operating temperature , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

[10]  J. Appels,et al.  High voltage thin layer devices (RESURF devices) , 1979, 1979 International Electron Devices Meeting.

[11]  H. Shichijo,et al.  off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown , 2007, IEEE Transactions on Electron Devices.

[12]  James Stasiak,et al.  Trap creation in silicon dioxide produced by hot electrons , 1989 .

[13]  A. Gnudi,et al.  TCAD predictions of linear and saturation HCS degradation in STI-based LDMOS transistors stressed in the impact-ionization regime , 2013, 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[14]  Wolfgang Fichtner,et al.  Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility , 2002 .

[15]  Sameer Pendharkar,et al.  Current status and future trends in silicon power devices , 2010, 2010 International Electron Devices Meeting.

[16]  Tibor Grasser,et al.  Impact of the carrier distribution function on hot-carrier degradation modeling , 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[17]  S. Pendharkar,et al.  Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[18]  W. Fulop,et al.  Calculation of avalanche breakdown voltages of silicon p-n junctions , 1967 .

[19]  R. Gillon,et al.  Universal Test Structure and Characterization Method for Bias-Dependent Drift Series Resistance of HV MOSFETs , 2002, 32nd European Solid-State Device Research Conference.

[20]  H. C. Tuan,et al.  Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS , 2011, 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.

[21]  K. Olasupo,et al.  Time dependent breakdown of ultrathin gate oxide , 2000 .

[22]  C. Jungemann,et al.  Comprehensive analysis of the degradation of a lateral DMOS due to hot carrier stress , 2009, 2009 IEEE International Integrated Reliability Workshop Final Report.

[23]  Chenming Hu,et al.  Optimum doping profile for minimum ohmic resistance and high-breakdown voltage , 1979 .

[24]  K.K. Ng,et al.  Analysis of the gate-voltage-dependent series resistance of MOSFET's , 1986, IEEE Transactions on Electron Devices.

[25]  Giuseppe Croce,et al.  Simulation of off-state degradation at high temperature in High Voltage NMOS transistor with STI architecture , 2010, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[26]  K. Chatty,et al.  A 120V 180nm High Voltage CMOS smart power technology for system-on-chip integration , 2010, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[27]  J. Shih,et al.  An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors , 2009, IEEE Transactions on Device and Materials Reliability.

[28]  C. T. Kirk,et al.  A theory of transistor cutoff frequency (fT) falloff at high current densities , 1962, IRE Transactions on Electron Devices.

[29]  Karl Hess,et al.  Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability , 2001, VLSI Design.

[30]  G. Groeseneken,et al.  A reliable approach to charge-pumping measurements in MOS transistors , 1984, IEEE Transactions on Electron Devices.

[31]  P. Gassot,et al.  Accumulation region length impact on 0.18µm CMOS fully-compatible lateral power MOSFETs with Shallow Trench Isolation , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[32]  J. McPherson,et al.  Complementary model for intrinsic time-dependent dielectric breakdown in SiO2 dielectrics , 2000 .

[33]  Kuo-Ming Wu,et al.  Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors , 2009, IEEE Transactions on Electron Devices.

[34]  Frederic Monsieur,et al.  High voltage devices in advanced CMOS technologies , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[35]  D. Varghese,et al.  Towards a universal model for hot carrier degradation in DMOS transistors , 2010, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[36]  J.D. Plummer,et al.  Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors , 1980, IEEE Transactions on Electron Devices.

[37]  S Pendharkar,et al.  Temperature Dependence of the Threshold Voltage Shift Induced by Carrier Injection in Integrated STI-Based LDMOS Transistors , 2011, IEEE Electron Device Letters.

[38]  J. Mitros,et al.  High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[39]  J. Bude,et al.  Thresholds of impact ionization in semiconductors , 1992 .

[40]  M. Vermandel,et al.  Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage , 2001, 31st European Solid-State Device Research Conference.

[41]  G. Groos,et al.  Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures , 2005, IEEE Transactions on Electron Devices.

[42]  A. W. Ludikhuize,et al.  Kirk effect limitations in high voltage IC's , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[43]  K. Benaissa,et al.  New cost-effective integration schemes enabling analog and high-voltage design in advanced CMOS SOC technologies , 2010, 2010 Symposium on VLSI Technology.

[44]  A. Gnudi,et al.  Hot-carrier stress induced degradation in Multi-STI-Finger LDMOS: An experimental and numerical insight , 2010, 2010 Proceedings of the European Solid State Device Research Conference.

[45]  Antonio Gnudi,et al.  Analysis of HCS in STI-based LDMOS transistors , 2010, 2010 IEEE International Reliability Physics Symposium.

[46]  V. Huard,et al.  Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature , 2009, 2009 IEEE International Reliability Physics Symposium.

[47]  A. Gnudi,et al.  TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors , 2013, IEEE Transactions on Electron Devices.

[48]  Xing Zhou,et al.  A physically-based semi-empirical effective mobility model for MOSFET compact I- V modeling , 2001 .

[49]  M. Alam,et al.  on-State Hot Carrier Degradation in Drain-Extended NMOS Transistors , 2010, IEEE Transactions on Electron Devices.

[50]  Kimimori Hamada,et al.  Wide-voltage SOI-BiCDMOS technology for high-temperature automotive applications , 2011, 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.

[51]  Adrianus Willem Ludikhuize,et al.  A review of RESURF technology , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[52]  K. Shirai,et al.  Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC's , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[53]  Sameer Pendharkar,et al.  Integrating power devices into silicon roadmaps , 2006 .

[54]  Karl Hess,et al.  Reliability scaling issues for nanoscale devices , 2003 .

[55]  A. Gnudi,et al.  Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors , 2011, IEEE Transactions on Electron Devices.

[56]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[57]  P. Hower,et al.  Two-Carrier Current Saturation in a Lateral Dmos , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[58]  A. Gnudi,et al.  Investigation on the temperature dependence of the HCI effects in the rugged STI-based LDMOS transistor , 2010, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[59]  Karl Hess,et al.  Impact of scaling on CMOS IC failure rate and design rules for reliability , 2000, 7th International Workshop on Computational Electronics. Book of Abstracts. IWCE (Cat. No.00EX427).

[60]  T. Efland,et al.  A Rugged LDMOS for LBC5 Technology , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[61]  Yan-Kuin Su,et al.  Effects of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors , 2006 .

[62]  F. M. Bufler,et al.  Gate Current Calculations Using Spherical Harmonic Expansion of Boltzmann Equation , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[63]  P. Moens,et al.  Characterization of Total Safe Operating Area of Lateral DMOS Transistors , 2006, IEEE Transactions on Device and Materials Reliability.

[64]  R. Zingg,et al.  On the specific on-resistance of high-voltage and power devices , 2004, IEEE Transactions on Electron Devices.

[65]  Martin Knaipp,et al.  Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors , 2008, IET Circuits Devices Syst..

[66]  A. Gnudi,et al.  Explanation of the Rugged LDMOS Behavior by Means of Numerical Analysis , 2009, IEEE Transactions on Electron Devices.

[67]  A. Gnudi,et al.  Full understanding of hot-carrier-induced degradation in STI-based LDMOS transistors in the impact-ionization operating regime , 2011, 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.

[68]  P. Gassot,et al.  Solutions to improve flatness of Id-Vd curves of rugged nLDMOS , 2011, 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.