Symmetric Varactor in 130-nm CMOS for Frequency Multiplier Applications

A symmetric varactor (SVAR) in 130-nm digital complementary metal-oxide-semiconductor (CMOS) for frequency multiplier applications with the maximum cutoff frequency of ~320 GHz and a dynamic cutoff frequency of ~125 GHz is demonstrated. To demonstrate the generation of odd-order harmonics and suppression of even-order ones, an SVAR was measured at the pumping frequency of 900 MHz. The measured third-order harmonic power is more than 25 dB higher than that for the second order. Harmonic balance simulations showed that the SVAR pumped by a 50-GHz signal source can generate a 150-GHz third-harmonic output signal with 15.8-dB minimum conversion loss at the input power of 7.8 dBm. The SVAR can be integrated with other (CMOS) components to generate millimeter-wave signals.

[1]  Jan Stake,et al.  Heterostructure-barrier-varactor design , 2000 .

[2]  S. Simon Wong,et al.  Analysis and optimization of accumulation-mode varactor for RF ICs , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[3]  J. Gerber,et al.  A systematic scheme for power amplifier design using a multi-harmonic loadpull simulation technique , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[4]  M. Sadeghi,et al.  A 0.2-W Heterostructure Barrier Varactor Frequency Tripler at 113 GHz , 2007, IEEE Electron Device Letters.

[5]  Haifeng Xu,et al.  High-$Q$ Thick-Gate-Oxide MOS Varactors With Subdesign-Rule Channel Lengths for Millimeter-Wave Applications , 2008, IEEE Electron Device Letters.

[6]  Chih-Ming Hung,et al.  High-Q capacitors implemented in a CMOS process for low-power wireless applications , 1998 .

[7]  Sebastian Magierowski,et al.  Differentially tunable varactor with built-in common-mode rejection , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[8]  M. Krach,et al.  Schottky diode tripler for 210 GHz , 2000 .

[9]  P.R. Gray,et al.  A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  K. O.,et al.  Complementary Antiparallel Schottky Barrier Diode Pair in a 0.13- $\mu \hbox{m}$ Logic CMOS Technology , 2008, IEEE Electron Device Letters.

[11]  Ruonan Han,et al.  Progress and Challenges Towards Terahertz CMOS Integrated Circuits , 2010, IEEE Journal of Solid-State Circuits.