Analysis of Analog Comparators Using a 6-Bit Flash ADC Architecture

This paper is based on the design of a 6-bit, 2.5 GS/s flash analog-to-digital converter (ADC). Lower power consumption is a prime objective in this paper. As analog comparators are the basic building blocks of any ADC, this work makes an insight into static and dynamic latched analog comparators and also draws a comparison between different works based on various parameters. Thereafter, it uses the optimized design amongst these comparators for flash ADC design. Power-delay characteristics as well as noise parameters such as offset voltage and kickback noise of the comparators are calculated keeping 1 V supply and a detailed analysis is done. Simulations are made in CADENCE using 45 nm CMOS technology yielding a SNDR of 57.7 dB, SFDR of 61 dB and FoM of 15 fJ/conv-step at Nyquist frequency of 2.5 GHz with an input frequency of 20 MHz and supply voltage 1 V. The power consumption is seen to be 2.4 mW with INL and DNL of 0.4 LSB and 0.2 LSB at the sampling frequency of 2.5 GS/s.

[1]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[2]  Yong-bin Kim,et al.  A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator , 2011, Analog Integrated Circuits and Signal Processing.

[3]  Degang Chen,et al.  Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Un-Ku Moon,et al.  Digitally synthesized stochastic flash ADC using only standard digital cells , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[5]  T. Nirschl,et al.  Yield and speed optimization of a latch-type voltage sense amplifier , 2004, IEEE Journal of Solid-State Circuits.

[6]  Denis C. Daly,et al.  A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Yi Xie,et al.  A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Daehwa Paik,et al.  A low-noise self-calibrating dynamic comparator for high-speed ADCs , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[9]  Un-Ku Moon,et al.  A 6b stochastic flash analog-to-digital converter without calibration or reference ladder , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[10]  Eisse Mensink,et al.  A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  Tsung-Han Tsai,et al.  An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Aparna Jayakumar,et al.  A 7-bit 500-MHz flash ADC , 2014, 2014 First International Conference on Computational Systems and Communications (ICCSC).

[13]  Reza Lotfi,et al.  Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Yukihiro Fujimoto,et al.  A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture , 1993 .