A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy

Built-in self-repair (BISR) technique is a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) component is a core component in a BISR design. This paper presents a BIRA scheme for RAMs with two-level redundancy, i.e., spare rows, spare columns, and spare words. A compressed local bitmap is used to collect faulty information for redundancy allocation. Then an efficient redundancy analysis algorithm based on the compressed local bitmap is proposed to allocate redundancy. Experimental results show that the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the proposed redundancy analysis algorithm approaches to that of the exhaustive search algorithm. Also, area overhead of the proposed BIRA scheme is low. It is only about 2% for an 8K × 64-bit RAM with three spare rows, three spare columns, and two spare words.

[1]  Keiichi Higeta,et al.  Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  Hiroki Koike,et al.  A 30-ns 64-Mb DRAM with built-in self-test and self-repair function , 1992 .

[3]  Jin-Fu Li,et al.  Memory fault diagnosis by syndrome compression , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Chin-Long Wey,et al.  On the Repair of Redundant RAM's , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Jin-Fu Li,et al.  A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.

[6]  Sy-yen Kuo,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987, IEEE Design & Test of Computers.

[7]  Joseph Rayhawk,et al.  At-speed built-in self-repair analyzer for embedded word-oriented memories , 2004, 17th International Conference on VLSI Design. Proceedings..

[8]  Yervant Zorian.  Embedded memory test and repair: infrastructure IP for SOC yield , 2002, Proceedings. International Test Conference.

[9]  Jin-Fu Li,et al.  A simulator for evaluating redundancy analysis algorithms of repairable embedded memories , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[10]  Steffen Paul,et al.  Memory built-in self-repair using redundant words , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Jin-Fu Li,et al.  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs , 2006, 2006 IEEE International Test Conference.

[12]  Y. Zorian.  Infrastructure IP for SOC , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[13]  Jin-Fu Li,et al.  A built-in self-repair design for RAMs with 2-D redundancy , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Jin-Fu Li,et al.  A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[18]  Dilip K. Bhavsar.  An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[19]  Jin-Fu Li,et al.  A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM , 2002, J. Electron. Test..

[20]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[21]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[23]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..