NAND GATE USING FINFET FOR NANOSCALE TECHNOLOGY

In this paper we propose Double gate transistors (FinFETs) are the substitutes for bulk CMOS evolving from a single gate devices into three dimensional devices with multiple gates (double gate, triple gate or quadruple-gate devices). The main drawback of using CMOS transistors are high power consumption and high leakage current. Enormous progress has been made to scale transistors to even smaller dimensions to obtain fast switching transistors, as well as to reduce the power consumption. Even though the device characteristics are improved, high active leakage remain a problem. Leakage is found to contribute more amount of total power consumption in power-optimized FinFET logic circuits. This paper mainly deals with the various logic design styles to obtain the Leakage power savings through the judicious use of FinFET logic styles.