A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm which can enhance the NoC communication performance with minimal energy overhead. In particular, our proposed NoC architecture exploits the following two features: i) self-reconfigurable bidirectional channels to increase the effective bandwidth and ii) express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. A deadlock-free and traffic-aware dynamic routing algorithm is further developed for the proposed architecture, which can take advantage of the increased flexibility in the proposed architecture. Both the channels self-reconfiguration and routing decisions are made in a distributed fashion, based on a function of the localized traffic conditions, in order to maximize the performance and minimize the energy costs at the macroscopic level. Our simulation results show that the proposed approach can reduce the network latency by 30\% -80\% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15\% power overhead.

[1]  Radu Marculescu,et al.  "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[3]  Babak Falsafi,et al.  DBmbench: fast and accurate database workload representation on modern microarchitecture , 2005, CASCON.

[4]  Jörg Henkel,et al.  Configurable links for runtime adaptive on-chip communication , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[6]  N.K. Jha,et al.  Toward Ideal On-Chip Communication Using Express Virtual Channels , 2008, IEEE Micro.

[7]  Andrew B. Kahng,et al.  ORION 2.0: A Power-Area Simulator for Interconnection Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Chi-Ying Tsui,et al.  A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[10]  Radu Marculescu,et al.  Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Srinivas Devadas,et al.  Oblivious Routing in On-Chip Bandwidth-Adaptive Networks , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

[12]  Bill Lin,et al.  Destination-based adaptive routing on 2D mesh networks , 2010, 2010 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

[13]  Onur Mutlu,et al.  Express Cube Topologies for on-Chip Interconnects , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[14]  Natalie D. Enright Jerger,et al.  DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[15]  Chifeng Wang,et al.  Congestion-aware Network-on-Chip router architecture , 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

[16]  Yu Hen Hu,et al.  A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Vincenzo Catania,et al.  Neighbors-on-Path: A New Selection Strategy for On-Chip Networks , 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.