A high-gain complementary metal-oxide semiconductor op amp using composite cascode stages

In this work, a complementary metal-oxide semiconductor (CMOS) op amp design using composite cascode stages is reported. The design follows the classic Widlar architecture and is fabricated on a 0.25 μm CMOS process. The measured gain of 117 dB is comparable to that achieved in bipolar designs in this architecture. This design is suited for precision instrumentation applications where high gain, low input offset voltage and small cell size are important. It provides a common-mode input range of −1 to 0.7 V using±1 V power supplies with a quiescent current of 55 μA. The use of the composite cascode also allows for dominant pole compensation with a single capacitor. A phase margin of 43° is achieved with a 3.5 pF compensation capacitor. The resulting cell size for the core op-amp circuit is approximately 24 × 16 mils, including large common centroid input devices that achieve an input offset voltage in the 1 mV range.

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