High-speed architectures for Reed-Solomon decoders

New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck in the Berlekamp-Massey algorithm is in the iterative computation of discrepancies followed by the updating of the error-locator polynomial. This bottleneck is eliminated via a series of algorithmic transformations that result in a fully systolic architecture in which a single array of processors computes both the error-locator and the error-evaluator polynomials. In contrast to conventional Berlekamp-Massey architectures in which the critical path passes through two multipliers and 1+[log/sub 2/,(t+1)] adders, the critical path in the proposed architecture passes through only one multiplier and one adder, which is comparable to the critical path in architectures based on the extended Euclidean algorithm. More interestingly, the proposed architecture requires approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm. For block-interleaved Reed-Solomon codes, embedding the interleaver memory into the decoder results in a further reduction of the critical path delay to just one XOR gate and one multiplexer, leading to speed-ups of as much as an order of magnitude over conventional architectures.

[1]  Hsie-Chia Chang,et al.  New serial architecture for the Berlekamp-Massey algorithm , 1999, IEEE Trans. Commun..

[2]  H.C. Chang,et al.  A Reed-Solomon Product-Code (RS-PC) decoder for DVD applications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[3]  S. Whitaker,et al.  Reed-Solomon VLSI codec for advanced television , 1991, IEEE Trans. Circuits Syst. Video Technol..

[4]  C. B. Shung,et al.  A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications , 1998 .

[5]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering , 1989, IEEE Trans. Acoust. Speech Signal Process..

[6]  Herbert O. Burton Inversionless decoding of binary BCH codes , 1971, IEEE Trans. Inf. Theory.

[7]  Stephen B. Wicker,et al.  Reed-Solomon Codes and Their Applications , 1999 .

[8]  Trieu-Kien Truong,et al.  VLSI design of inverse-free Berlekamp-Massey algorithm , 1991 .

[9]  Janice Nelson,et al.  Systolic architectures for decoding Reed-Solomon codes , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[10]  Po Tong A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[11]  Elwyn R. Berlekamp,et al.  Algebraic coding theory , 1984, McGraw-Hill series in systems science.

[12]  James L. Massey,et al.  Shift-register synthesis and BCH decoding , 1969, IEEE Trans. Inf. Theory.

[13]  W. Wilhelm A new scalable VLSI architecture for Reed-Solomon decoders , 1999 .

[14]  R. Wells Applied Coding and Information Theory for Engineers , 1998 .

[15]  K. J. RAY LIU Algorithm-Based Low-Power and High-Performance Multimedia Signal Processing , 2001 .

[16]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[17]  R. Blahut Theory and practice of error control codes , 1983 .

[18]  S. Wicker Error Control Systems for Digital Communication and Storage , 1994 .

[19]  Hyunchul Shin,et al.  An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs , 1997 .

[20]  J.L. Massey,et al.  Theory and practice of error control codes , 1986, Proceedings of the IEEE.

[21]  J. H. Yuen,et al.  A VLSI design of a pipeline Reed-Solomon decoder , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.