Design Optimization for Minimal Crosstalk in Differential Interconnect

[1]  James E. Jaussi,et al.  Future Microprocessor Interfaces: Analysis, Design and Optimization , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[2]  Ramesh Harjani,et al.  A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os , 2010, IEEE Custom Integrated Circuits Conference 2010.

[3]  Beom-Taek Lee,et al.  High speed differential I/O overview and design challenges on Intel enterprise server platforms , 2011, 2011 IEEE International Symposium on Electromagnetic Compatibility.

[4]  A. Hajimiri,et al.  Cancellation of crosstalk-induced jitter , 2006, IEEE Journal of Solid-State Circuits.

[5]  Ramesh Harjani,et al.  FEXT Crosstalk Cancellation for High-Speed Serial Link Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[6]  Martin H. Graham,et al.  Book Review: High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham: (Prentice-Hall, 1993) , 1993, CARN.

[7]  R. Mooney,et al.  An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[8]  Xiaoning Ye Intentional and un-intentional far end crosstalk cancellation in high speed differential link , 2011, 2011 IEEE International Symposium on Electromagnetic Compatibility.