75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques

Memory interfaces for high-speed graphics systems have reached the 4 to 6 Gb/s/pin regime with GDDR4 and the introduction of GDDR5 [1–4] at chip densities up to 512Mb. To satisfy the demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. In this paper, a 7Gb/s/pin 1Gb GDDR5 DRAM with an array architecture for fast column access, a boosting transmitter, multiple voltage (VINT) domains to control on chip power noise, and a high-speed internal VINT power generator system are presented. This 1Gb GDDR5 memory device is fabricated in a conventional 75nm DRAM process and characterized for a 7Gb/s/pin data transfer rate at 1.5V.

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