Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine

The accuracte cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM) based compute-in-memory inference engine. To tighten the distribution of the cells of each state, we developed a two-step write-verify scheme within the limited number of iteration, which was tested on a test vehicle based on HfO2 RRAM array to realize 2-bit per cell. The conductance of the cells are gathered in the targeted range within 10 loops of set and reset process for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper-bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intemediate state cells under relatively high read voltage (e.g. 0.2V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5-bit ADC that is required for 128×128 array with 2-bit per cell.

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