Voltage-island driven floorplanning considering level-shifter positions

Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.

[1]  I-Min Liu,et al.  Post-placement voltage island generation under performance requirement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[2]  Yao-Wen Chang,et al.  An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Tadahiro Kuroda,et al.  Utilizing surplus timing for power reduction , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[4]  Radu Marculescu,et al.  Architecting voltage islands in core-based system-on-a-chip designs , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[5]  Yici Cai,et al.  Corner block list representation and its application to floorplan optimization , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Narayanan Vijaykrishnan,et al.  Temperature-aware voltage islands architecting in system-on-chip design , 2005, 2005 International Conference on Computer Design.

[7]  Wai-Kei Mak,et al.  Voltage Island Generation under Performance Requirement for SoC Designs , 2007, 2007 Asia and South Pacific Design Automation Conference.

[8]  Hung-Yi Liu,et al.  Voltage Island Aware Floorplanning for Power and Timing Optimization , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[9]  Evangeline F. Y. Young,et al.  Network flow-based power optimization under timing constraints in MSV-driven floorplanning , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  John M. Cohn,et al.  Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[11]  Evangeline F. Y. Young,et al.  Post-Placement Voltage Island Generation , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.