Layout compaction for yield optimization via critical area minimization

This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as critical area. Instead of assuming that the critical area could probably be present everywhere in the layout, the algorithm first finds where this area can actually exist, and then attempts to minimize it. The algorithm takes benefit from a fast multi-layer critical area computation to extract the rectangles that compose it. Afterwards, the extracted rectangles are involved into the layer minimization process which is the second phase of the compaction procedure to minimize their area. A new formulation of the layer minimization problem is used in such a way that the critical area minimization adds neither extra variables nor extra constraints to the original compaction algorithm. The algorithm has been tested on actual layouts.