IMPACT: A high-level synthesis system for low power control-flow intensive circuits

In this paper, we present a comprehensive high-level synthesis system that is geared towards reducing power consumption in control-flow intensive circuits. An iterative improvement algorithm is at the heart of the system. The algorithm searches the design space by handling scheduling, module selection, resource sharing and multiplexer network restructuring simultaneously. The scheduler performs concurrent loop optimization and implicit loop unrolling. It minimizes the expected number of cycles of the schedule without compromising on the minimum and maximum schedule lengths. A fast simulation technique based on trace manipulation aids power estimation in driving synthesis in the right direction. Experimental results demonstrate power reduction of up to 85% with minimal overhead in area over area-optimized designs operating at 5 V.

[1]  Niraj K. Jha,et al.  Register-transfer level estimation techniques for switching activity and power consumption , 1996, ICCAD 1996.

[2]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Sujit Dey,et al.  Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications , 1994, 31st Design Automation Conference.

[4]  R. Composano,et al.  Path-based scheduling for synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[5]  A.A. Jerraya,et al.  AMICAL: An interactive high level synthesis environment , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[6]  Nikil D. Dutt,et al.  A comprehensive estimation technique for high-level synthesis , 1995, Proceedings of the Eighth International Symposium on System Synthesis.

[7]  Abhijit Chatterjee,et al.  Synthesis of low power linear DSP circuits using activity metrics , 1994, Proceedings of 7th International Conference on VLSI Design.

[8]  Niraj K. Jha,et al.  Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[10]  Chong-Min Kyung,et al.  FAMOS: an efficient scheduling algorithm for high-level synthesis , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Louise Trevillyan,et al.  Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Bozena Kaminska,et al.  Functional synthesis of digital systems with TASS , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Kazutoshi Wakabayashi,et al.  A resource sharing and control synthesis method for conditional branches , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[14]  S. Katkoori,et al.  Profile-driven behavioral synthesis for low-power VLSI systems , 1995, IEEE Design & Test of Computers.

[15]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Niraj K. Jha,et al.  An iterative improvement algorithm for low power data path synthesis , 1995, ICCAD.

[17]  M. Potkonjak,et al.  Energy efficient implementation of linear systems on programmable processors , 1995, VLSI Signal Processing, VIII.

[18]  Chien-Liang Liu,et al.  Low power multiplexer decomposition , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[19]  J. Rabaey,et al.  Behavioral Level Power Estimation and Exploration , 1997 .

[20]  Sujit Dey,et al.  Glitch analysis and reduction in register transfer level power optimization , 1996, DAC '96.

[21]  C. L. Liu,et al.  A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Nikil D. Dutt,et al.  1995 high level synthesis design repository , 1995, Proceedings of the Eighth International Symposium on System Synthesis.

[23]  Sujit Dey,et al.  Clock Period Optimization During Resource Sharing and Assignment , 1994, 31st Design Automation Conference.