A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier

A single chip 2.4 Gb/s optical receiver IC for the next generation access system integrates a preamplifier, automatic offset and gain controller (AGC), phase-locked loop (PLL) and 1:8 demultiplexer (DEMUX) using a 0.15 /spl mu/m bulk CMOS process, realizing low cost and low power consumption. The preamplifier reduces the effect of noise caused by substrate crosstalk and has 5.9 GHz bandwidth and 59 dB/spl Omega/ transimpedance gain. Input current from the photodiode is transformed into a voltage by the preamplifier and then amplified by the AGC circuit. The PLL circuit extracts the clock from input data and the DEMUX circuit converts input serial data into 8 b parallel data.

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