An architecture for parallel multipliers

A novel architecture for parallel multipliers is proposed based on a previously published architecture that used five-counters as the basic building block. The architecture removes the redundancy associated with an incompletely spanned output range of the five-counter cell, by changing the building block to a two-bit full adder. This cell has the same number of inputs, but produces an output that completely spans the output dynamic range. It is shown that a dynamic logic implementation of the five-counter has a 46% hardware increase over the two-bit full adder cell proposed for this architecture. The resulting two-bit adder cell architecture shows an almost 50% decrease in silicon area and almost a 30% decrease in evaluation time compared to the five-counter cell architecture.<<ETX>>