Efficient design of continuous time linear equalization for loss dominated digital links

Signal degradation in high-speed data links can be mitigated by means of channel equalization. One preferred choice in conjunction with other techniques is the Continuous Time Linear Equalizer (CTLE) due to its effectiveness. Although CTLE being common technology, adaptation of design parameters regularly relies on trial and error. This work proposes a simple, yet very effective method for CTLE design, referred to as matched CTLE (mCTLE). It advocates channel characterization in the frequency domain which is crucial for the placement of CTLE poles and zeros. Demonstration and discussion based on typical interconnect topologies illustrate the novel approach in the context of existing literature.