A 0.5V GFSK 200μW limiter/demodulator with bulk-driven technique for Low-IF bluetooth

This paper presents a low-voltage IF processor including a limiter and a DLL-based demodulator for bluetooth receiver. The limiter amplifies the received IF signals with constant envelope. The demodulator detects and manipulates the edges of the IF signal. To achieve 0.5V operation the bulk-driven technique are extensively used in amplifier design nd more digital-like operations are used in demodulator. With the IF frequency of 3MHz, the power consumption of the limiter and demodulator is only 200μW. The core area is 0.36 mm2 using a standard 0.18-μm CMOS process. Measurement result shows that a 18.7-dB input signal-to-noise ratio is obtained for a 0.1% bit error rate.

[1]  Liang-Hung Lu,et al.  An Experimental Ultra-Low-Voltage Demodulator in 0.18-$\mu$ m CMOS , 2009, IEEE Transactions on Microwave Theory and Techniques.

[2]  Po-Chiun Huang,et al.  A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[3]  Edgar Sanchez-Sinencio,et al.  A GFSK demodulator for low-IF Bluetooth receiver , 2003 .

[4]  Hong-Sing Kao,et al.  A Delay-Line-Based GFSK Demodulator for Low-IF Receivers , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  Chan-Hong Park,et al.  A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[6]  Chorng-Kuang Wang,et al.  A 2-V CMOS 455 kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[7]  Sameer R. Sonkusale,et al.  A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[8]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[9]  Chorng-Kuang Wang,et al.  A 2-V 10.7-MHz CMOS limiting amplifier/RSSI , 2000, IEEE Journal of Solid-State Circuits.

[10]  P. Kinget,et al.  0.5-V analog circuit techniques and their application in OTA and filter design , 2005, IEEE Journal of Solid-State Circuits.

[11]  Ulrich L. Rohde,et al.  Communications Receivers: DSP, Software Radios, and Design , 2000 .

[12]  J.P.F. Glas.  A differential FM detector for low-IF radios , 1999, Gateway to 21st Century Communications Village. VTC 1999-Fall. IEEE VTS 50th Vehicular Technology Conference (Cat. No.99CH36324).