论文信息 - A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool

This paper presents a new folding algorithm applied to an automatic layout generation tool. Most of transistors sizing algorithms propose continuous sizing. Nevertheless, in row-based layout synthesis, the variation of transistor sizes may cause non-uniform cell heights that may lead to significant waste of layout area. The proposed folding approach leads to a very simple algorithm that is able to obtain very good results.

Ricardo Reis | Cristiano Lazzari | José Luís Almada Güntzel | Fabricio B. Bastian

[1] Krzysztof S. Berezowski. Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[2] Sung-Mo Kang,et al. An efficient transistor folding algorithm for row-based CMOS layout design , 1997, DAC.

[3] Ricardo Reis,et al. A transistor sizing method applied to an automatic layout generation tool , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[4] Cristiano Lazzari,et al. A New Macro-cell Generation Strategy for three metal layer CMOS Technologies , 2003, VLSI-SOC.

[5] John P. Hayes,et al. XPRESS: a cell layout generator with integrated transistor folding , 1996, Proceedings ED&TC European Design and Test Conference.

[6] John P. Hayes,et al. Optimal 2-D cell layout with integrated transistor folding , 1998, ICCAD '98.

[7] Ricardo Augusto da Luz Reis. Power and Timing Driven Physical Design Automation , 2003, PATMOS.