Realistic Workload Characterization and Analysis for Networks-on-Chip Design

As silicon device scaling trends have simultaneously increased transistor density while reducing component costs, architectures incorporating multiple communicating components are becoming more common. In these systems, networks-on-chip (NOCs) connect the components for communication and NOC design is critical to the performance and efficiency of the system. Typically, in NOC design traditional synthetic workloads are used to characterize the performance of the system. Previous work shows, however, that these traditional synthetic workloads do not accurately represent the characteristics of realistic network traffic. In this paper we propose the analysis of realistic traffic via a set of new workload characteristics. We show that these characteristics more accurately correlate with network congestion in realistic workloads than traditional metrics.

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