A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems

Predictable arbitration policies, such as Time Division Multiplexing (TDM) and Round-Robin (RR), are used to provide firm real-time guarantees to clients sharing a single memory resource (DRAM) between the multiple memory clients in multi-core real-time systems. Traditional centralized implementations of predictable arbitration policies in a shared memory bus or interconnect are not scalable in terms of the number of clients. On the other hand, existing distributed memory interconnects are either globally arbitrated, which do not offer diverse service according to the heterogeneous client requirements, or locally arbitrated, which suffers from larger area, power and latency overhead. Moreover, selecting the right arbitration policy according to the diverse and dynamic client requirements in reusable platforms requires a generic re-configurable architecture supporting different arbitration policies. The main contributions in this paper are: (1) We propose a novel generic, scalable and globally arbitrated memory tree (GSMT) architecture for distributed implementation of several predictable arbitration policies. (2) We present an RTL-level implementation of Accounting and Priority assignment (APA) logic of GSMT that can be configured with five different arbitration policies typically used for shared memory access in real-time systems. (3) We compare the performance of GSMT with different centralized implementations by synthesizing the designs in a 40 nm process. Our experiments show that with 64 clients GSMT can run up to four times faster than traditional architectures and have over 51% and 37% reduction in area and power consumption, respectively.

[1]  ResourcesKen Chapman Multiplexer Design Techniques for Datapath Performance with Minimized Routing , 2012 .

[2]  Alois Knoll,et al.  Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Maarten Wiggers,et al.  A Priority-Based Budget Scheduler with Conservative Dataflow Model , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[4]  Pieter van der Wolf,et al.  SoC infrastructures for predictable system integration , 2011, 2011 Design, Automation & Test in Europe.

[5]  Tomas Henriksson,et al.  Heterogeneous multi-core platform for consumer multimedia applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Kees G. W. Goossens,et al.  Architectures and modeling of predictable memory controllers for improved system integration , 2011, 2011 Design, Automation & Test in Europe.

[7]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[8]  Martin Schoeberl,et al.  A Time-Predictable Memory Network-on-Chip , 2014, WCET.

[9]  Kees van Berkel,et al.  Multi-core for mobile phones , 2009, DATE.

[10]  George F. Riley,et al.  Round-robin Arbiter Design and Generation , 2002, 15th International Symposium on System Synthesis, 2002..

[11]  Costas Courcoubetis,et al.  Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip , 1991, IEEE J. Sel. Areas Commun..

[12]  Kees G. W. Goossens,et al.  Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[13]  Francisco J. Cazorla,et al.  Timing effects of DDR memory systems in hard real-time multicore architectures , 2013, ACM Trans. Embed. Comput. Syst..

[14]  Kees Goossens,et al.  Chapter 15 INTERCONNECT AND MEMORY ORGANIZATION IN SOCS FOR ADVANCED SET-TOP BOXES AND TV Evolution, Analysis, and Trends , 2005 .

[15]  Kees Goossens,et al.  Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems , 2011 .

[16]  Emmanouil Kalligeros,et al.  Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[17]  C.H. van Berkel,et al.  Multi-core for mobile phones , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[18]  Luca Benini,et al.  A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters , 2011, 2011 Design, Automation & Test in Europe.

[19]  Kees G. W. Goossens,et al.  Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Gerard J. M. Smit,et al.  Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core System , 2012, 2012 15th Euromicro Conference on Digital System Design.

[21]  Kees G. W. Goossens,et al.  A reconfigurable real-time SDRAM controller for mixed time-criticality systems , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[22]  Alan Burns,et al.  Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[23]  Kees G. W. Goossens,et al.  Channel trees: Reducing latency by sharing time slots in time-multiplexed Networks on Chip , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[24]  Neil C. Audsley,et al.  Prefetching across a shared memory tree within a Network-on-Chip architecture , 2013, 2013 International Symposium on System on Chip (SoC).

[25]  Kees Goossens,et al.  Memory Controllers for Real-Time Embedded Systems , 2012 .

[26]  Kees G. W. Goossens,et al.  Dynamic Command Scheduling for Real-Time Memory Controllers , 2014, 2014 26th Euromicro Conference on Real-Time Systems.