A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering

Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, field-programmable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales as <inline-formula><tex-math notation="LaTeX">$O(\omega ^2)$</tex-math> </inline-formula> with the filter width <inline-formula><tex-math notation="LaTeX">$\omega$</tex-math></inline-formula> . In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just <inline-formula> <tex-math notation="LaTeX">$O(1)$</tex-math></inline-formula> operations for any arbitrary <inline-formula> <tex-math notation="LaTeX">$\omega$</tex-math></inline-formula>. The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.

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