Signaling Analysis and Optimal Channel Data Rates for High-Performance FPGA Interfaces

The study of the optimal data rates of high-speed channels supported by typical high-performance FPGA chips is presented. First, the representative channels are grouped into distinct categories that have drastically dissimilar characteristics. Consequently, the range of the channel operating data rates are expected to be significantly different. Special circuitries of various complexity are often implemented in the transmitters and receivers to mitigate the channel attenuation and enable the link to operate at the desired data rates. This paper attempts to shed a light on the optimal intrinsic channel data rates. Based on the signaling power, receiver sensitivity and the channel frequency responses, the range or optimal signaling rates of the channels are derived for each category. Finally, the paper summarizes the main differences of the channels in terms of characteristics, transceiver complexity, and optimal data rates when the high-speed links are implemented in suitable semiconductor technology.