A reconfigurable and high precision VLSI architecture for Fast Fourier Transform
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[1] Michael L. Bushnell,et al. Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[2] U. Jagdhold,et al. A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM , 2004, IEEE Journal of Solid-State Circuits.
[3] An-Yeu Wu,et al. Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems , 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.
[4] Viktor Öwall,et al. Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[5] Yu-Wei Lin,et al. A 1-GS/s FFT/IFFT processor for UWB applications , 2005, IEEE Journal of Solid-State Circuits.
[6] Xiaojin Li,et al. A Low Power and Small Area FFT Processor for OFDM Demodulator , 2007, IEEE Transactions on Consumer Electronics.
[7] An Pan,et al. Low-cost reconfigurable VLSI architecture for fast fourier transform , 2008, IEEE Transactions on Consumer Electronics.
[8] Myung Hoon Sunwoo,et al. New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[9] Chen-Yi Lee,et al. A dynamic scaling FFT processor for DVB-T applications , 2004 .
[10] J. Tukey,et al. An algorithm for the machine calculation of complex Fourier series , 1965 .