Scheduling tests for VLSI systems under power constraints

This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: (1) scheduling equal length tests with power constraints and (2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. Finally, a minimum cover table approach is used to find an optimum schedule of power compatible tests.

[1]  Kurt Keutzer,et al.  Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Dieter Jungnickel,et al.  Graphs, Networks, and Algorithms , 1980 .

[3]  Melvin A. Breuer,et al.  Test Schedules for VLSI Circuits Having Built-In Test Hardware , 1986, IEEE Transactions on Computers.

[4]  Mario J. Gonzalez.  Deterministic Processor Scheduling , 1977, CSUR.

[5]  R. Roth,et al.  Computer Solutions to Minimum-Cover Problems , 1969, Oper. Res..

[6]  Edward J. McCluskey,et al.  Introduction to the theory of switching circuits , 1965 .

[7]  B. Ricco,et al.  A novel approach to cost-effective estimate of power dissipation in CMOS ICs , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[8]  Charles R. Kime,et al.  An Efficient Algorithm for Finding an Irredundant Set Cover , 1974, JACM.

[9]  Wen-Ben Jone,et al.  A Scheme for Overlaying Concurrent Testing of VLSI Circuits , 1989, 26th ACM/IEEE Design Automation Conference.

[10]  R. E. Tulloss,et al.  BIST and boundary-scan for board level test: test program pseudocode , 1989, [1989] Proceedings of the 1st European Test Conference.

[11]  Kewal K. Saluja,et al.  Test Scheduling and Control for VLSI Built-In Self-Test , 1988, IEEE Trans. Computers.

[12]  Donald Leo Dietmeyer,et al.  Logic design of digital systems , 1971 .

[13]  F. Dresig,et al.  Simulation and reduction of CMOS power dissipation at logic level , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[14]  Andrzej Krasniewski,et al.  Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules , 1985, ITC.

[15]  H.J. De Man,et al.  PRITI: Estimation of maximal currents and current derivatives in complex CMOS circuits using activities waveforms , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[16]  Najmi T. Jarwala,et al.  A Framework for Boundary-Scan Based System Test and Diagnosis , 1992, Proceedings International Test Conference 1992.

[17]  Kewal K. Saluja,et al.  TEST SCHEDULING IN TESTABLE VLSI CIRCUITS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[18]  Frank Harary,et al.  Graph Theory , 2016 .

[19]  A. A. Shneider,et al.  Classification analysis of heuristic algorithms for graph coloring , 1984, Cybernetics.

[20]  Vishwani D. Agrawal,et al.  Power constraint scheduling of tests , 1994, Proceedings of 7th International Conference on VLSI Design.

[21]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.