Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.

[1]  Single-chip interpolating time counter with 200-ps resolution and 43-s range , 1996, Quality Measurement: The Indispensable Bridge between Theory and Reality (No Measurements? No Science! Joint Conference - 1996: IEEE Instrumentation and Measurement Technology Conference and IMEKO Tec.

[2]  Ryszard Szplet,et al.  Time-to-digital converter with direct coding and 100ps resolution , 1995 .

[3]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[4]  A. El Gamal,et al.  Architecture of field-programmable gate arrays , 1993, Proc. IEEE.

[5]  A. Rothermel,et al.  Analog Phase Measuring Circuit for Digital CMOS-ICS , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[6]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines in the digitization of short time intervals , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[7]  T. Ohsugi,et al.  TMC-a CMOS time to digital converter VLSI , 1989 .

[8]  T. K. Ohska,et al.  1.2 GHz GaAs shift register IC for dead-time-less TDC application , 1989 .

[9]  J. Kalisz,et al.  Error analysis and design of the Nutt time-interval digitiser with picosecond resolution , 1987 .