Simulation-based techniques for dynamic test sequence compaction

Simulation-based techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partially-specified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in the partially-specified test sequence in order to increase the number of faults detected by the sequence. Significant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator.

[1]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Irith Pomeranz,et al.  On generating compact test sequences for synchronous sequential circuits , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[3]  Anand Raghunathan,et al.  Bottleneck removal algorithm for dynamic compaction and test cycles reduction , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[4]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[5]  Irith Pomeranz,et al.  Dynamic test compaction for synchronous sequential circuits using static compaction techniques , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[6]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[7]  Anand Raghunathan,et al.  Dynamic test sequence compaction for sequential circuits , 1996, Proceedings of 9th International Conference on VLSI Design.

[8]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Kewal K. Saluja,et al.  Methods for dynamic test vector compaction in sequential test generation , 1996, Proceedings of 9th International Conference on VLSI Design.

[10]  Elizabeth M. Rudnick,et al.  A genetic approach to test application time reduction for full scan and partial scan circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.

[11]  R Bevacqua,et al.  Implicit test sequences compaction for decreasing test application cost , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[12]  Janak H. Patel,et al.  Test compaction for sequential circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.