Constructive multi-phase test point insertion for scan-based BIST

This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.

[1]  Sunil Jain,et al.  Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.

[2]  Balakrishnan Krishnamurthy A Dynamic Programming Approach to the Test Point Insertion Problem , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Elizabeth M. Rudnick,et al.  An observability enhancement approach for improved testability and at-speed test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Vishwani D. Agrawal,et al.  A Statistical Theory of Digital Circuit Testability , 1990, IEEE Trans. Computers.

[5]  Hans-Joachim Wunderlich,et al.  Multiple distributions for biased random test patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[6]  B. Koenemann LFSR-coded test patterns for scan designs , 1991 .

[7]  Arthur D. Friedman,et al.  Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.

[8]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[9]  John A. Waicukauski,et al.  Two-dimensional test data decompressor for multiple scan designs , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[10]  Janusz Rajski,et al.  Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-le , 1991, 1991, Proceedings. International Test Conference.

[11]  Daniel Brand,et al.  Synthesis of pseudo-random pattern testable designs , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[12]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[13]  A. J. Briers,et al.  Random Pattern Testability by Fast Fault Simulation , 1986, International Test Conference.

[14]  M. Koudil,et al.  Automatic test point insertion for pseudo-random testing , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[15]  Kwang-Ting Cheng,et al.  Timing-driven test point insertion for full-scan and partial-scan BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[16]  J. R. Fox Test-point Condensation in the Diagnosis of Digital Circuits , 1977 .

[17]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[18]  Dhiraj K. Pradhan,et al.  A novel pattern generator for near-perfect fault-coverage , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[19]  Hans-Joachim Wunderlich PROTEST: A Tool for Probabilistic Testability Analysis , 1985, DAC 1985.

[20]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[21]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[22]  Nur A. Touba,et al.  Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[23]  Michael Randolph Garey,et al.  Johnson: "computers and intractability , 1979 .

[24]  John A. Waicukauski,et al.  A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation , 1985, ITC.