In this paper, a power amplifier (PA) using power cell switching (PCS) technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at power back-off. Distributed active transformers (DATs) are employed as splitter, combiner and DC bias feed to partition the power requirements among the parallelized power cells. Individual cell can be dynamically turned on/off in response to the desired output power. Post-layout simulations were conducted in the 3GPP LTE band at 2.535GHz. The most significant improvement is obtained at 7 dB back-off from 27dBm where PAE is increased from 2.8% to 5%.