Design techniques for variability mitigation

As the fabrication technology migrated towards the nanometre scale, 22 nm and beyond, yield enhancement has become one of the challenges facing the integrated circuits design community. Delay and power consumption of the manufactured chips deviate from their predesigned values due to process, voltage and temperature (PVT) variations. This deviation can lead to a considerable loss in yield and reliability. In this paper, we classify and survey the approaches developed to mitigate the PVT variations on the circuit and architectural levels.

[1]  Duncan G. Elliott,et al.  Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Antonio Rubio,et al.  A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs , 2009, Microelectron. J..

[3]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[4]  Sandip Kundu,et al.  A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors , 2015, ACM Trans. Embed. Comput. Syst..

[5]  Bing Li,et al.  Statistical Static Timing Analysis , 2012 .

[6]  Javier Garrido Salas,et al.  Thermal Testing on Reconfigurable Computers , 2000, IEEE Des. Test Comput..

[7]  Youngsoo Shin,et al.  Retiming Pulsed-Latch Circuits With Regulating Pulse Width , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Todd M. Austin,et al.  Ultra low-cost defect protection for microprocessor pipelines , 2006, ASPLOS XII.

[9]  Laurent Fesquet,et al.  Programmable/Stoppable Oscillator Based on Self-Timed Rings , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[10]  David Blaauw,et al.  Timing yield enhancement through soft edge flip-flop based design , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[11]  M.A. Horowitz,et al.  Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[12]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[13]  Jiun-In Guo,et al.  Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[14]  Yehea I. Ismail,et al.  SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[16]  David Blaauw,et al.  Reducing pipeline energy demands with local DVS and dynamic retiming , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[17]  John W. Lockwood,et al.  An adaptive frequency control method using thermal feedback for reconfigurable hardware applications , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[18]  John W. Lockwood,et al.  Adaptive Thermoregulation for Applications on Reconfigurable Devices , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[19]  Sachin S. Sapatnekar,et al.  Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).