A 9-bit 123-MS/s swiched-current pipelined ADC with OP feedback and offset current cancellation

This paper presents a 9-bit 123-MS/s switched-current pipelined analog-to-digital converter (ADC) with low transmission error and small channel charge injection. To decrease the transmission error, a current mirror with op feedback is used. Furthermore, both dummy switch and offset current cancellation are adopted to reduce the channel charge injection. As the proposed pipelined ADC is implemented in TSMC 1P6M 0.18-μm CMOS technology, the simulation results show that the signal-to-noise and distortion (SNDR), differential nonlinearity, integral nonlinearity, and power consumption are 55.56 dB, -0.21~+0.19 LSB, -0.1~+0.37 LSB, and 45.5 mW, respectively, at the input frequency of 5MHz, sampling rate of 123 MS/s, and the supply voltage of 1.8 V. Notify that the figure of merit of the proposed pipelined ADC is about 0.78pJ/conversion at the operational current range of -20μA~+20μA.

[1]  Yasuhiro Sugimoto,et al.  A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  H.C. Luong,et al.  A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture , 2007, IEEE Journal of Solid-State Circuits.

[3]  Krzysztof Wawryn,et al.  Low power current mode 8 1.5-bit stages pipelined a/d converter , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[4]  Chung-Yu Wu,et al.  The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Ying Wu,et al.  A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[6]  Behnam Sedighi,et al.  An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS , 2007, ISCAS.

[7]  Xiang Liu,et al.  A capacitor-mismatch-insensitive switch-capacitor amplifier for Pipeline ADC , 2007, 2007 7th International Conference on ASIC.

[8]  E. Abdel-Raheem,et al.  A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends , 2005, PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005..

[9]  D. G. Nairn,et al.  High-resolution, current-mode A/D convertors using active current mirrors , 1988 .

[10]  Ding-Lan Shen,et al.  A negative resistance compensated switching current sampled-and-hold circuit , 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

[11]  Guo-Ming Sung,et al.  A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.