Evolutionary design of hash function pairs for network filters

Graphical abstractDisplay Omitted HighlightsPipelined reconfigurable hash function with parallel computation is proposed for IP address filtering in field-programmable gate arrays.The evolutionary algorithm fine-tunes the reconfigurable hash function for the given set of Internet Protocol addresses.The proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional hash functions. Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions.