UML activity diagram swimlanes in logic controller design
暂无分享,去创建一个
[1] Edmund M. Clarke,et al. Model Checking , 1999, Handbook of Automated Reasoning.
[2] Thomas Kropf. Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems , 1999 .
[3] Marian Adamski,et al. Reduction of the Microinstruction Length in the designing process of Microprogrammed Controllers , 2009 .
[4] Iwona Grobelna,et al. Decomposition, validation and documentation of control process specification in form of a Petri net , 2014, 2014 7th International Conference on Human System Interactions (HSI).
[5] Hassane Alla,et al. Discrete, continuous, and hybrid Petri Nets , 2004 .
[6] Iwona Grobelna,et al. Deadlock detection in Petri nets: One trace for one deadlock? , 2014, 2014 7th International Conference on Human System Interactions (HSI).
[7] Kwan Hee Han,et al. Rapid virtual prototyping of PLC-based control system , 2010, ICIA 2010.
[8] Iwona Grobelna,et al. Formal verification of embedded logic controller specification with computer deduction in temporal logic , 2011 .
[9] Marian Adamski,et al. Application of comparability graphs in decomposition of Petri nets , 2014, 2014 7th International Conference on Human System Interactions (HSI).
[10] Thomas Kropf,et al. Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.
[11] Marian Adamski,et al. Hardware behavioural modelling, verification and synthesis with UML 2.x activity diagrams , 2012, PDeS.