Area Efficient VLSI Design with Cells of Controllable Complexity

Applications where there may be a large amount of data movement are notoriously dqficult to implement using VLSI. In this paper we have presented a new, hybrid, architecture which combines the advantages of a high wire organization with those of a nearest neighbor systolic organization. Our approach is to consider the use of relatively large, complex, cells, using high wire organization, as the building block for a systolic array. In such arrays, we may consider communication in two distinct levels - intracell level and intercell level. Intracell communication may use "long" wires but intercell communicarion always uses "short" wires. Here the speed requirements of the user determines the cell size. We have explored the application of perimeter sorting in this paper. The approach is also applicable to other areas such as data routing and FFT.