Design and Analysis of Low Power Single Edge Triggered D Flip Flop

Low power flip-flops are crucial for the design of low-power digital systems. As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are scaled down to nanometer ranges, Complementary MOS (CMOS) circuit’s total Power consumption has a new definition. Due to integration of millions of components and shrinking process technology, nowadays leakage power tends to play a major role in total power consumption. This fact has motivated a lot of researchers and technologists to choose leakage current minimization as their future work. Proper selection of flip-flops is necessary in order to satisfy low power and high performance circuit. In this paper investigation of conventional and proposed single edge triggered flip-flop is done with comparisons of average power, delay and power delay product which claims that proposed design is suitable for low power applications.

[1]  Ch. Daya Sagar,et al.  Design of a Low Power Flip-Flop Using MTCMOS Technique , 2012 .

[2]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[3]  Hussain Al-Asaad,et al.  A New Low Power High Performance Flip-Flop , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[4]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[5]  Fei Qiao,et al.  A Novel Low-Power and High-Speed Master-Slave D Flip-Flop , 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

[6]  Rached Tourki,et al.  A new low-power N fold flip-flop with output enable , 2012, 2012 6th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT).

[7]  Mirza Tariq Beg,et al.  Analysis of different techniques for low power Single Edge Triggered Flip Flops , 2011, 2011 World Congress on Information and Communication Technologies.

[8]  Hussain Al-Asaad,et al.  Survey and Evaluation of Low-Power Flip-Flops , 2006, CDES.

[9]  Dr,et al.  A Modified ScanD Flip-flop Design to Reduce Test Power . , 2008 .

[10]  Manoj Sharma,et al.  An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop , 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

[11]  R. Wong,et al.  Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology , 2011, IEEE Transactions on Nuclear Science.

[12]  Randy H. Katz,et al.  Contemporary Logic Design , 2004 .

[13]  Tripti Sharma,et al.  SET D-flip flop design for portable applications , 2011, India International Conference on Power Electronics 2010 (IICPE2010).

[14]  Davide De Caro,et al.  New clock-gating techniques for low-power flip-flops , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[15]  Jinn-Shyan Wang,et al.  A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[16]  Vladimir Stojanovic,et al.  Comparative analysis of latches and flip-flops for high-performance systems , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[17]  Peiyi Zhao,et al.  Low power and high speed explicit-pulsed flip-flops , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[18]  Robert W. Brodersen,et al.  Analysis and design of low-energy flip-flops , 2001, ISLPED '01.