Test Data Compression Using Selective Sparse Storage
暂无分享,去创建一个
[1] Aiman H. El-Maleh. Test data compression for system-on-a-chip using extended frequency-directed run-length code , 2008, IET Comput. Digit. Tech..
[2] Sybille Hellebrand,et al. Data compression for multiple scan chains using dictionaries with corrections , 2004 .
[3] Krishnendu Chakrabarty,et al. How effective are compression codes for reducing test data volume? , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[4] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[5] Nur A. Touba,et al. An efficient test vector compression scheme using selective Huffman coding , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Krishnendu Chakrabarty,et al. Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[7] Zhang Ling,et al. Test data compression using four-coded and sparse storage for testing embedded core , 2010, ICA3PP 2010.
[8] Montserrat Ros,et al. A hamming distance based VLIW/EPIC code compression technique , 2004, CASES '04.
[9] Mehrdad Nourani,et al. RL-huffman encoding for test compression and power reduction in scan applications , 2005, TODE.
[10] D. Huffman. A Method for the Construction of Minimum-Redundancy Codes , 1952 .
[11] Shianling Wu,et al. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG , 2008, IEEE Design & Test of Computers.
[12] Nur A. Touba,et al. Reducing test data volume using LFSR reseeding with seed compression , 2002, Proceedings. International Test Conference.
[13] Xiaolang Yan,et al. Test data compression using extended frequency-directed run length code based on compatibility , 2010 .
[14] Srivaths Ravi,et al. Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Krishnendu Chakrabarty,et al. System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] Janusz Rajski,et al. Low-Power Scan Operation in Test Compression Environment , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Emmanouil Kalligeros,et al. Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores , 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Emmanouil Kalligeros,et al. Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Krishnendu Chakrabarty,et al. A unified approach to reduce SOC test data volume, scan power and testing time , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Katherine Shu-Min Li,et al. Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Lung-Jen Lee,et al. Test Data Compression Using Multi-dimensional Pattern Run-length Codes , 2010, J. Electron. Test..
[22] Mark Mohammad Tehranipoor,et al. Nine-coded compression technique for testing embedded cores in SoCs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] Nilanjan Mukherjee,et al. Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[24] Emmanouil Kalligeros,et al. Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[25] Emmanouil Kalligeros,et al. Optimal Selective Huffman Coding for Test-Data Compression , 2007, IEEE Transactions on Computers.
[26] Bashir M. Al-Hashimi,et al. Variable-length input Huffman coding for system-on-a-chip test , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Krishnendu Chakrabarty,et al. Test data compression for IP embedded cores using selective encoding of scan slices , 2005, IEEE International Conference on Test, 2005..
[28] Krishnendu Chakrabarty,et al. Test Data Compression Using Selective Encoding of Scan Slices , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[29] Prabhat Mishra,et al. Bitmask-Based Code Compression for Embedded Systems , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[30] J.H. Patel,et al. Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[31] Aiman H. El-Maleh,et al. Efficient test compression technique based on block merging , 2008, IET Comput. Digit. Tech..
[32] Mango Chia-Tso Chao,et al. Theoretical analysis for low-power test decompression using test-slice duplication , 2010, 2010 28th VLSI Test Symposium (VTS).
[33] Rohit Kapur,et al. Efficient compression of deterministic patterns into multiple PRPG seeds , 2005, IEEE International Conference on Test, 2005..