Architecture for High Performance Systems
暂无分享,去创建一个
Vikas Agarwal | Karthikeyan Sankaralingam | Doug Burger | Stephen W. Keckler | Premkishore Shivakumar | Charles R. Moore | Nitya Ranganathan | C. R. Moore | S. Keckler | K. Sankaralingam | D. Burger | V. Agarwal | N. Ranganathan | P. Shivakumar
[1] S. Keckler,et al. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[2] R. Nagarajan,et al. A design space evaluation of grid processor architectures , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.
[3] Hiroshi Nakamura,et al. Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.